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january 2007 hys64d[16/32/64][300/301/320][g/h]u?5?c hys72d[32/64][300/301/320][g/h]u?5?c hys64d[16/32/64][300/301/320][g/h]u?6?c hys72d[32/64][300/301/320][g/h]u?6?c 184- pin unbuffered ddr sdram modules udimm ddr sdram internet data sheet rev. 1.11
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys[64/72]d[16/32/64][300 /301/320][g/h]u?[5/6]?c unbuffered ddr sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 09152006-1lhy-n6g4 hys64d[16/32/64][300/301/320][g/h]u?5?c , hys72d[32/64][300/301/320][g/h]u?5?c, hys64d[16/32/64][300/301/320][g/h]u?6?c , hys72d[32/64][300/301/320][g/h]u?6?c revision history: 2007-01, rev. 1.11 page subjects (major changes since last revision) all qimonda update all adapted internet edition previous revision: rev. 1.1
internet data sheet 3 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules overview 1overview 1.1 features ? 184-pin unbuffered double data rate sdram (ecc and non-pari ty) for pc and server main memory applications ? one rank 16m x 64, 32m 64, 32m 72 and two ranks 64m 64, 64m 72 organization ? jedec standard double data rate sync hronous drams (ddr sdram) single +2.5v ( 0.2v) power supply and +2.6v ( 0.1v) ppower supply for ddr400 ? built with 256 mbit ddr sdram in p-tsopii-66-1 package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. ? jedec standard reference layout ? gold plated contacts ? ddr400 speed grade supported 1.2 description the hys64d[16/32/64][300/301/ 320][g/h]u?5?c, hys7 2d[32/64][300/30 1/320][g/h]u?5?c, hys64d[16/32/64][300/301/320][g /h]u?6?c and hys72d[32/64][300/301/320][g/h]u?6?c are industry standard 184-pin unbuffered double data rate sdram (udimm) organized as 16m 64, 32m 64 and 64m 64 for non-parity and 32m 72 and 64m 72 for ecc main memory applications. the memory array is designed with 256mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the printed circuit board. the dimms feature serial presence detect (spd) based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer table 1 performance product type speed code ? 5 ? 6unit module speed grade ddr400b ddr333b ? component module pc3200?3033 pc2700?2533 ? max. clock frequency @ cl = 3 f ck3 200 166 mhz @ cl = 2.5 f ck2.5 166 166 mhz @ cl = 2 f ck2 133 133 mhz
internet data sheet 4 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules overview table 2 ordering information for lead-free products product type 2) compliance code description sdram technology pc3200 (cl=3) hys64d16301gu?5?c pc3200u?30330?c0 o ne rank 128mb dimm 256 mbit ( 16) hys64d32300gu?5?c pc3200u?30330?a0 o ne rank 256mb dimm 256 mbit ( 8) hys72d32300gu?5?c pc3200u?30330?a0 one rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320gu?5?c pc3200u?30330?b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320gu?5?c pc3200u?30330?b0 two ranks 512mb ecc-dimm 256 mbit ( 8) pc2700 (cl=2.5) hys64d16301gu?6?c pc2700u?25330?c0 o ne rank 128mb dimm 256 mbit ( 16) hys64d32300gu?6?c pc2700u?25330?a0 o ne rank 256mb dimm 256 mbit ( 8) hys72d32300gu?6?c pc2700u?25330?a0 one rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320gu?6?c pc2700u?25330?b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320gu?6?c pc2700u?25330?b0 two ranks 512mb ecc-dimm 256 mbit ( 8) table 3 ordering information for lead-free (rohs 1) compliant products) 1) rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2 002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmiu m, hexavalent chromium, po lybrominated biphenyls and polybrominated biphenyl ethers. product type 2) 2) all part numbers end with a place code designating the silic on-die revision. reference information available on request. example: hys72d32000hu-6-c, indicating rev. c dies are used for sdram components. the compliance code is printed on the module labels describing the speed sort (for example ?pc2700?), the latencies and sp d code definition (for example ?20330? means cas latency of 2.0 clocks, row-column-delay (rcd) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0 ), and the raw card used for this module. compliance code description sdram technology pc3200 (cl=3) hys64d16301hu?5?c pc3200u?30330?c0 one rank 128mb dimm 256 mbit ( 16) hys64d32300hu?5?c pc3200u?30330?a0 one rank 256mb dimm 256 mbit ( 8) hys72d32300hu?5?c pc3200u?30330?a0 o ne rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320hu?5?c pc3200u?30330?b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320hu?5?c pc3200u?30330?b0 tw o ranks 512mb ecc-dimm 256 mbit ( 8) pc2700 (cl=2.5) hys64d16301hu?6?c pc2700u?25330?c0 one rank 128mb dimm 256 mbit ( 16) hys64d32300hu?6?c pc2700u?25330?a0 one rank 256mb dimm 256 mbit ( 8) hys72d32300hu?6?c pc2700u?25330?a0 o ne rank 256mb ecc-dimm 256 mbit ( 8) hys64d64320hu?6?c pc2700u?25330?b0 two ranks 512mb dimm 256 mbit ( 8) hys72d64320hu?6?c pc2700u?25330?b0 tw o ranks 512mb ecc-dimm 256 mbit ( 8)
internet data sheet 5 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules pin configuration 2 pin configuration the pin configuration of the unbuffered ddr sdram dimm is listed by function in table 4 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 5 and table 6 respectively. the pin numbering is depicted in figure 1 . table 4 pin configuration of udimm pin# name pin type buffer type function clock signals 137 ck0 i sstl clock signals 2:0 nc nc ? 16 ck1 i sstl 76 ck2 i sstl 138 ck0 i sstl complement clock signals 2:0 nc nc ? 17 ck1 i sstl 75 ck2 i sstl 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 157 s0 i sstl chip select rank 0 158 s1 i sstl chip select rank 1 note: 2-rank module nc nc ? note: 1-rank module 154 ras i sstl row address strobe 65 cas i sstl column address strobe 63 we i sstl write enable address signals 59 ba0 i sstl bank address bus 2:0 52 ba1 i sstl 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl 32 a5 i sstl 125 a6 i sstl 29 a7 i sstl 122 a8 i sstl address bus 11:0 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl 106 dq13 i/o sstl 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl 114 dq20 i/o sstl 117 dq21 i/o sstl table 4 pin configuration of udimm (cont?d) pin# name pin type buffer type function
internet data sheet 6 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules pin configuration 121 dq22 i/o sstl data bus 63:0 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl 150 dq38 i/o sstl 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl 166 dq53 i/o sstl 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl 174 dq60 i/o sstl 175 dq61 i/o sstl table 4 pin configuration of udimm (cont?d) pin# name pin type buffer type function 178 dq62 i/o sstl data bus 63:0 179 dq63 i/o sstl 44 cb0 i/o sstl check bit 0 note: ecc type module nc nc ? note: non-ecc module 45 cb1 i/o sstl check bit 1 note: ecc type module nc nc ? note: non-ecc module 49 cb2 i/o sstl check bit 2 note: ecc type module nc nc ? note: non-ecc module 51 cb3 i/o sstl check bit 3 note: ecc type module nc nc ? note: non-ecc module 134 cb4 i/o sstl check bit 4 note: ecc type module nc nc ? note: non-ecc module 135 cb5 i/o sstl check bit 5 note: ecc type module nc nc ? note: non-ecc module 142 cb6 i/o sstl check bit 6 note: ecc type module nc nc ? note: non-ecc module 144 cb7 i/o sstl check bit 7 note: ecc type module nc nc ? note: non-ecc module 5 dqs0 i/o sstl data strobe bus 7:0 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl 78 dqs6 i/o sstl 86 dqs7 i/o sstl 47 dqs8 i/o sstl data strobe 8 note: ecc type module nc nc ? note: non-ecc module table 4 pin configuration of udimm (cont?d) pin# name pin type buffer type function
internet data sheet 7 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules pin configuration 97 dm0 i sstl data mask bus 7:0 107 dm1 i sstl 119 dm2 i sstl 129 dm3 i sstl 149 dm4 i sstl 159 dm5 i sstl 169 dm6 i sstl 177 dm7 i sstl 140 dm8 i sstl data mask 8 note: ecc type module nc nc ? note: non-ecc module eeprom 92 scl i cmos serial bus clock 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply table 4 pin configuration of udimm (cont?d) pin# name pin type buffer type function 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwr ? power supply 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss gnd ? ground plane other pins 82 v ddid ood v dd identification 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected table 4 pin configuration of udimm (cont?d) pin# name pin type buffer type function
internet data sheet 8 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules pin configuration figure 1 pin configuration 184-pin, udimm table 5 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 6 abbreviations for buffer type abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. mppd0030 pin 093 pin 095 pin 097 pin 099 pin 101 pin 103 pin 105 pin 107 pin 109 pin 111 - - - - - - - - - - pin 094 pin 096 pin 098 pin 100 pin 102 pin 104 pin 106 pin 108 pin 110 pin 112 - - - - - - - - - - v ss dq05 dm0 dq07 nc nc dq12 dm1 dq14 cke1/nc dq04 dq06 nc dq13 dq15 pin 114 pin 116 pin 118 pin 120 pin 122 pin 124 pin 126 pin 128 pin 130 pin 132 pin 134 pin 136 pin 138 pin 140 pin 142 pin 144 dq20 a11 a8 dq28 a3 cb4/nc ck0/nc dm8/nc cb06/nc cb7/nc - - - - - - - - - - - - - - - - pin 113 pin 115 pin 117 pin 119 pin 121 pin 123 pin 125 pin 127 pin 129 pin 131 pin 133 pin 135 pin 137 pin 139 pin 141 pin 143 nc a12/nc dq21 dm2 dq22 dq23 a6 dq29 dm3 dq30 dq31 cb5/nc ck0/nc v ss a10/ap v ddq - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v ref v ss dqs0 v dd nc v ss dq09 v ddq ck1 dq10 dq00 dq01 dq02 dq03 nc dq08 dqs1 ck1 v ss dq11 dq17 dq18 a5 dqs3 dq27 cb00/nc a0 ba1 - - - - - - - - - - - - - - - - cke0 dq16 dqs2 a9 a7 dq19 dq24 dq25 a04 dq26 a2 a1 cb01/nc dqs8/nc cb02/nc cb03/nc - - - - - - - - - - - - - - - - pin 145 pin 147 pin 149 pin 151 pin 153 pin 155 pin 157 pin 159 pin 161 pin 163 pin 165 pin 167 pin 169 pin 171 pin 173 pin 175 pin 177 pin 179 pin 181 pin 183 v ss dq37 dm4 dq39 dq44 dq45 s0 dm5 dq46 nc dq52 a13/nc dm6 dq51 nc dq61 dm7 dq63 sa0 sa2 - - - - - - - - - - - - - - - - - - - - dq36 dq38 ras s1/nc dq47 dq53 dq54 dq60 dq62 sa1 - - - - - - - - - - - - - - - - - - - - pin 146 pin 148 pin 150 pin 152 pin 154 pin 156 pin 158 pin 160 pin 162 pin 164 pin 166 pin 168 pin 170 pin 172 pin 174 pin 176 pin 178 pin 180 pin 182 pin 184 pin 002 pin 004 pin 006 pin 008 pin 010 pin 012 pin 014 pin 016 pin 018 pin 020 pin 022 pin 024 pin 026 pin 028 pin 030 pin 032 pin 034 pin 036 pin 038 pin 040 pin 042 pin 044 pin 046 pin 048 pin 050 pin 052 pin 001 pin 003 pin 005 pin 007 pin 009 pin 011 pin 013 pin 015 pin 017 pin 019 pin 021 pin 023 pin 025 pin 027 pin 029 pin 031 pin 033 pin 035 pin 037 pin 039 pin 041 pin 043 pin 045 pin 047 pin 049 pin 051 pin 054 pin 056 pin 058 pin 060 pin 062 pin 064 pin 066 pin 068 pin 070 pin 072 pin 074 pin 076 pin 078 pin 080 pin 082 pin 084 pin 086 pin 088 pin 090 pin 092 pin 053 pin 055 pin 057 pin 059 pin 061 pin 063 pin 065 pin 067 pin 069 pin 071 pin 073 pin 075 pin 077 pin 079 pin 081 pin 083 pin 085 pin 087 pin 089 pin 091 - - - - - - - - - - - - - - - - - - - - dqs4 dq35 dq41 dq42 dq48 ck2 dqs6 dq51 dq57 dqs7 dq59 nc scl dq32 dq33 dq34 ba0 dq40 we cas dqs5 dq43 nc dq49 ck2 v ddq dq50 v ss dq56 v dd dq58 v ss sda - - - - - - - - - - - - - - - - - - - - v ddq v ss v ddq v ss v dd v ss v dd v ss v ddq v ss v ddq v ss v dd v ss v ddid v ddq v ss v ddq v dd v ddq v ss v dd v ss v ddq v ss v ddq v dd v ss v ddq v ss v ddq v dd v ddq v ss v ddq v ddspd
internet data sheet 9 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules pin configuration table 7 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 128mb 16m 64 1 16m 16 4 13/2/9 8k 64 ms 7.8 s 256mb 32m 64 1 32m 88 13/2/10 8k 64ms7.8 s 256mb 32m 72 1 32m 89 13/2/10 8k 64ms7.8 s 512mb 64m 64 2 32m 8 16 13/2/10 8k 64 ms 7.8 s 512mb 64m 72 2 32m 8 18 13/2/10 8k 64 ms 7.8 s
internet data sheet 10 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 8 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq +0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg ?55 ? +150 c? power dissipation (per sdram component) p d ?1 ? w? short circuit output current i out ?50? ma? table 9 electrical characteristics and dc operating conditions parameter symbol values unit note/ test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 0?0v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v f ck 166 mhz 4) input reference voltage v ref v ddq / 2 ? 50 mv v ddq / 2 v ddq / 2 + 50 mv v f ck >166mhz 2)4) i/o termination voltage (system) v tt v ref ? 0.04 ? v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 ? v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ?0.3 ? v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ?0.3 ? v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 ? v ddq + 0.6 v 8)6)
internet data sheet 11 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics vi-matching pull-up current to pull-down current vi ratio 0.71 ? 1.4 ? 7) input leakage current i i ?2 ? 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 ? 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ? ? ?16.2 ma v out = 1.95 v 8) output low current, normal strength driver i ol 16.2 ? ? ma v out = 0.35 v 8) 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2 % v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal terminatio n resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between th e input level on ck and the input level on ck . 7) the ration of the pull-up current to the pull-down current is specified for the same temperat ure and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per ddr sdram component table 9 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/ test condition 1) min. typ. max.
internet data sheet 12 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics 3.2 current conditions and specification table 10 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs chan ging once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; powe r-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs c hanging once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs c hanging once per clock cycle; 50 % of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs c hanging once per clock cycle; 50 % of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
internet data sheet 13 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics table 11 i dd specification for pc3200 part number & organization hys64d16301hu?5?c hys64d16301gu?5?c hys64d32300hu?5?c hys64d32300gu?5?c hys72d32300hu?5?c hys72d32300gu?5?c hys64d64320hu?5?c hys64d64320gu?5?c hys72d64320hu?5?c hys72d64320gu?5?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently depending on actual to dq loading capacitance. 2) test condition fo r maximum values: v dd =2.7v, t a =10c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. typ. max. i dd0 300 360 560 720 630 810 864 1080 972 1215 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 380 440 640 800 720 900 944 1160 1062 1305 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 16 20 32 40 36 45 64 80 72 90 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 120 144 240 288 270 324 480 576 540 648 ma 5) i dd2q 80 112 160 224 180 252 320 448 360 504 ma 5) i dd3p 52 72 104 144 117 162 208 288 234 324 ma 5) i dd3n 172 216 304 360 342 405 608 720 684 810 ma 5) i dd4r 400 480 680 800 765 900 984 1160 1107 1305 ma 3)4) i dd4w 400 520 720 840 810 945 1024 1200 1152 1350 ma 3) i dd5 560 760 1120 1520 1260 1710 1424 1880 1602 2115 ma 3) i dd6 6 11 11 22 13 25 22 45 25 50 ma ? i dd7 840 1000 1680 2000 1890 2250 1984 2360 2232 2655 ma 3)4)
internet data sheet 14 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics table 12 i dd specification for pc2700 part number & organization hys64d16301hu?6?c hys64d16301gu?6?c hys64d32300hu?6?c hys64d32300gu?6?c hys72d32300hu?6?c hys72d32300gu?6?c hys64d64320hu?6?c hys64d64320gu?6?c hys72d64320hu?6?c hys72d64320gu?6?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition fo r maximum values: v dd =2.7v, t a =10c 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?6 ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. typ. max. i dd0 260 300 480 600 540 675 736 904 828 1017 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 320 380 560 680 630 765 816 984 918 1107 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 16 20 32 40 36 45 64 80 72 90 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 100 340 200 240 225 270 400 480 450 540 ma 5) i dd2q 68 96 136 192 153 216 272 384 306 432 ma 5) i dd3p 44 60 88 120 99 135 176 240 198 270 ma 5) i dd3n 144 180 256 304 288 342 512 608 576 684 ma 5) i dd4r 340 400 560 680 630 765 816 984 918 1107 ma 3)4) i dd4w 360 440 600 720 675 810 856 1024 963 1152 ma 3) i dd5 480 640 960 1280 1080 1440 1216 1584 1368 1782 ma 3) i dd6 6 11 11 22 13 25 44 22 25 25 ma ? i dd7 720 860 1440 1720 1620 1935 1696 2024 1908 2277 ma 3)4)
internet data sheet 15 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics 3.3 ac characteristic table 13 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsopii 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )? min. ( t cl , t ch )? ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ?0.7 +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9)
internet data sheet 16 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qh ? t hp ? t qhs ?ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) active to autoprecharge delay t rap t rcd ?t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ?7.8?7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 65 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . table 13 ac timing - absolute specifications for pc3200 and pc2700 (cont?d) parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
internet data sheet 17 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules electrical characteristics 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih (ac) and v il (ac). 9) these parameters guarantee device timing, but they are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input sl ew rate specifications of th e device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 12) the maximum limit for this parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnar ound) degrades accordingly.
internet data sheet 18 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 4spdcontents this chapter lists all hexadecim al byte values stored in t he eeprom of the product s described in this da ta sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes whic h are defined during production. list of spd code tables ? table 14 ?spd codes for hys[64/72]d[ 16/32/64][300/301/320]gu?5?c? on page 18 ? table 15 ?spd codes for hys[64/72]d[ 16/32/64][300/301/320]gu?6?c? on page 22 ? table 16 ?spd codes for hys[64/72]d[16 /32/64][300/301/320]hu?5?c? on page 25 ? table 17 ?spd codes for hys[64/72]d[16 /32/64][300/301/320]hu?6?c? on page 28 table 14 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?5?c product type hys64d16301gu?5?c hys64d32300gu?5?c hys72d32300gu?5?c hys64d64320gu?5?c hys72d64320gu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 0d 4 number of column addresses 09 0a 0a 0a 0a 5 number of dimm ranks 01 01 01 02 02 6 data width (lsb) 40 40 48 40 48 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 50 11 error correction support 00 00 02 00 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 10 08 08 08 08 14 error checking sdram width 00 00 08 00 08
internet data sheet 19 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 1c 1c 1c 1c 1c 19 cs latency 01 01 01 01 01 20 write latency 02 02 02 02 02 21 dimm attributes 20 20 20 20 20 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c 3c 28 t rrdmin [ns] 28 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 28 31 module density per rank 20 40 40 40 40 32 t as, t cs [ns] 60 60 60 60 60 33 t ah, t ch [ns] 60 60 60 60 60 34 t ds [ns] 40 40 40 40 40 35 t dh [ns] 40 40 40 40 40 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 37 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 41 43 t ckmax [ns] 28 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 50 46 not used 00 00 00 00 00 table 14 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?5?c product type hys64d16301gu?5?c hys64d32300gu?5?c hys72d32300gu?5?c hys64d64320gu?5?c hys72d64320gu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 20 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 47 dimm pcb height 00 00 00 00 00 48 - 61 not used 00 00 00 00 00 62 spd revision 00 00 00 00 00 63 checksum of byte 0-62 e4 fd 0f fe 10 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx 73 part number, char 1 36 36 37 36 37 74 part number, char 2 34 34 32 34 32 75 part number, char 3 44 44 44 44 44 76 part number, char 4 31 33 33 36 36 77 part number, char 5 36 32 32 34 34 78 part number, char 6 33 33 33 33 33 79 part number, char 7 30 30 30 32 32 80 part number, char 8 31 30 30 30 30 81 part number, char 9 47 47 47 47 47 82 part number, char 10 55 55 55 55 55 83 part number, char 11 35 35 35 35 35 84 part number, char 12 43 43 43 43 43 85 part number, char 13 20 20 20 20 20 86 part number, char 14 20 20 20 20 20 87 part number, char 15 20 20 20 20 20 table 14 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?5?c product type hys64d16301gu?5?c hys64d32300gu?5?c hys72d32300gu?5?c hys64d64320gu?5?c hys72d64320gu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 21 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 88 part number, char 16 20 20 20 20 20 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 table 14 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?5?c product type hys64d16301gu?5?c hys64d32300gu?5?c hys72d32300gu?5?c hys64d64320gu?5?c hys72d64320gu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 22 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents table 15 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?6?c product type hys64d16301gu?6?c hys64d32300gu?6?c hys72d32300gu?6?c hys64d64320gu?6?c hys72d64320gu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 0d 4 number of column addresses 09 0a 0a 0a 0a 5 number of dimm ranks 01 01 01 02 02 6 data width (lsb) 40 40 48 40 48 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 70 11 error correction support 00 00 02 00 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 10 08 08 08 08 14 error checking sdram width 00 00 08 00 08 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 0c 0c 0c 0c 0c 19 cs latency 01 01 01 01 01 20 write latency 02 02 02 02 02 21 dimm attributes 20 20 20 20 20 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 00 27 t rpmin [ns] 48 48 48 48 48
internet data sheet 23 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 28 t rrdmin [ns] 30 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 2a 31 module density per rank 20 40 40 40 40 32 t as, t cs [ns] 75 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 75 34 t ds [ns] 45 45 45 45 45 35 t dh [ns] 45 45 45 45 45 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 48 43 t ckmax [ns] 30 30 30 30 30 44 t dqsqmax [ns] 2d 2d 2d 2d 2d 45 t qhsmax [ns] 55 55 55 55 55 46 not used 00 00 00 00 00 47 dimm pcb height 00 00 00 00 00 48 - 61 not used 00 00 00 00 00 62 spd revision 00 00 00 00 00 63 checksum of byte 0-62 e8 01 13 02 14 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx table 15 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?6?c product type hys64d16301gu?6?c hys64d32300gu?6?c hys72d32300gu?6?c hys64d64320gu?6?c hys72d64320gu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 24 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 73 part number, char 1 36 36 37 36 37 74 part number, char 2 34 34 32 34 32 75 part number, char 3 44 44 44 44 44 76 part number, char 4 31 33 33 36 36 77 part number, char 5 36 32 32 34 34 78 part number, char 6 33 33 33 33 33 79 part number, char 7 30 30 30 32 32 80 part number, char 8 31 30 30 30 30 81 part number, char 9 47 47 47 47 47 82 part number, char 10 55 55 55 55 55 83 part number, char 11 36 36 36 36 36 84 part number, char 12 43 43 43 43 43 85 part number, char 13 20 20 20 20 20 86 part number, char 14 20 20 20 20 20 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 table 15 spd codes for hys[64/72]d[16/32/64][300/301/320]gu?6?c product type hys64d16301gu?6?c hys64d32300gu?6?c hys72d32300gu?6?c hys64d64320gu?6?c hys72d64320gu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 25 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents table 16 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?5?c product type hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev . 0.0 rev. 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 0d 4 number of column addresses 09 0a 0a 0a 0a 5 number of dimm ranks 01 01 01 02 02 6 data width (lsb) 40 40 48 40 48 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 50 11 error correction support 00 00 02 00 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 10 08 08 08 08 14 error checking sdram width 00 00 08 00 08 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 1c 1c 1c 1c 1c 19 cs latency 01 01 01 01 01 20 write latency 02 02 02 02 02 21 dimm attributes 20 20 20 20 20 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c 3c
internet data sheet 26 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 28 t rrdmin [ns] 28 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 28 31 module density per rank 20 40 40 40 40 32 t as, t cs [ns] 60 60 60 60 60 33 t ah, t ch [ns] 60 60 60 60 60 34 t ds [ns] 40 40 40 40 40 35 t dh [ns] 40 40 40 40 40 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 37 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 41 43 t ckmax [ns] 28 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 50 46 not used 00 00 00 00 00 47 dimm pcb height 00 00 00 00 00 48 - 61 not used 00 00 00 00 00 62 spd revision 00 00 00 00 00 63 checksum of byte 0-62 e4 fd 0f fe 10 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufactur er location xx xx xx xx xx table 16 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?5?c product type hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev . 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 27 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 73 part number, char 1 36 36 37 36 37 74 part number, char 2 34 34 32 34 32 75 part number, char 3 44 44 44 44 44 76 part number, char 4 31 33 33 36 36 77 part number, char 5 36 32 32 34 34 78 part number, char 6 33 33 33 33 33 79 part number, char 7 30 30 30 32 32 80 part number, char 8 31 30 30 30 30 81 part number, char 9 48 48 48 48 48 82 part number, char 10 55 55 55 55 55 83 part number, char 11 35 35 35 35 35 84 part number, char 12 43 43 43 43 43 85 part number, char 13 20 20 20 20 20 86 part number, char 14 20 20 20 20 20 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revi sion code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturi ng date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 table 16 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?5?c product type hys64d16301hu?5?c hys64d32300hu?5?c hys72d32300hu?5?c hys64d64320hu?5?c hys72d64320hu?5?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 pc3200u? 30330 jedec spd revision rev. 0.0 rev . 0.0 rev. 0.0 rev . 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 28 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents table 17 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?6?c product type hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex 0 programmed spd bytes in e 2 prom 80 80 80 80 80 1 total number of bytes in e 2 prom 08 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 0d 4 number of column addresses 09 0a 0a 0a 0a 5 number of dimm ranks 01 01 01 02 02 6 data width (lsb) 40 40 48 40 48 7 data width (msb) 00 00 00 00 00 8 interface voltage levels 04 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 70 11 error correction support 00 00 02 00 02 12 refresh rate 82 82 82 82 82 13 primary sdram width 10 08 08 08 08 14 error checking sdram width 00 00 08 00 08 15 t ccd [cycles] 01 01 01 01 01 16 burst length supported 0e 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 04 18 cas latency 0c 0c 0c 0c 0c 19 cs latency 01 01 01 01 01 20 write latency 02 02 02 02 02 21 dimm attributes 20 20 20 20 20 22 component attributes c1 c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 00 27 t rpmin [ns] 48 48 48 48 48
internet data sheet 29 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 28 t rrdmin [ns] 30 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 2a 31 module density per rank 20 40 40 40 40 32 t as, t cs [ns] 75 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 75 34 t ds [ns] 45 45 45 45 45 35 t dh [ns] 45 45 45 45 45 36 - 40 not used 00 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 48 43 t ckmax [ns] 30 30 30 30 30 44 t dqsqmax [ns] 2d 2d 2d 2d 2d 45 t qhsmax [ns] 55 55 55 55 55 46 not used 00 00 00 00 00 47 dimm pcb height 00 00 00 00 00 48 - 61 not used 00 00 00 00 00 62 spd revision 00 00 00 00 00 63 checksum of byte 0-62 e8 01 13 02 14 64 manufacturer?s jedec id code (1) 7f 7f 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 00 00 72 module manufacturer location xx xx xx xx xx table 17 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?6?c product type hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 30 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules spd contents 73 part number, char 1 36 36 37 36 37 74 part number, char 2 34 34 32 34 32 75 part number, char 3 44 44 44 44 44 76 part number, char 4 31 33 33 36 36 77 part number, char 5 36 32 32 34 34 78 part number, char 6 33 33 33 33 33 79 part number, char 7 30 30 30 32 32 80 part number, char 8 31 30 30 30 30 81 part number, char 9 48 48 48 48 48 82 part number, char 10 55 55 55 55 55 83 part number, char 11 36 36 36 36 36 84 part number, char 12 43 43 43 43 43 85 part number, char 13 20 20 20 20 20 86 part number, char 14 20 20 20 20 20 87 part number, char 15 20 20 20 20 20 88 part number, char 16 20 20 20 20 20 89 part number, char 17 20 20 20 20 20 90 part number, char 18 20 20 20 20 20 91 module revision code 1x 1x 1x 1x 1x 92 test program revision code xx xx xx xx xx 93 module manufacturing date year xx xx xx xx xx 94 module manufacturing date week xx xx xx xx xx 95 - 98 module serial number xx xx xx xx xx 99 - 127 not used 00 00 00 00 00 table 17 spd codes for hys[64/72]d[16/32/64][300/301/320]hu?6?c product type hys64d16301hu?6?c hys64d32300hu?6?c hys72d32300hu?6?c hys64d64320hu?6?c hys72d64320hu?6?c organization 128mb 256mb 256mb 512mb 512mb 64 64 72 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 pc2700u? 25330 jedec spd revision rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 rev. 0.0 byte# description hex hex hex hex hex
internet data sheet 31 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules package outlines 5 package outlines figure 2 package outlines - raw card c 128 mbyte, 1 rank module a 4 0.1 a 0.1 bc 2.7 max. 133.35 b 0.15 a c 0.1 2.36 1 95 64.77 ?0.1 ac b = 1.27 x 120.65 2.175 6.62 6.35 49.53 92 3 min. 93 0.1 0.1 1.8 b ac 17.8 184 1.27 1 0.05 0.1 b a c detail of contacts 0.2 2.5 0.2 c 0.1 1.27 0.4 b 0.13 31.75 128.95 10 3.8 0.13 1) burr max. 0.4 allowed 1) on ecc modules only
internet data sheet 32 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules package outlines figure 3 package outline - raw card a 256 mbyte, 1 rank module 92 1 1.27 1 0.05 0.1 b a c detail of contacts 0.2 3 min. 2.5 0.2 3.8 93 0.13 0.1 1.8 a 0.1 c b 17.8 10 184 92 1.27 0.1 c 0.4 b 31.75 0.13 2.7 max. 6.62 0.1 1 2.36 64.77 95 x c b a ?0.1 6.35 120.65 1.27 = 2.175 49.53 92 0.1 4 0.1 a bc 128.95 133.35 b 0.15 a c a burr max. 0.4 allowed l-dim-184-32
internet data sheet 33 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules package outlines figure 4 package outline - raw card a 256 mbyte, 1 rank ecc module 1 92 0.13 1 0.05 1.27 0.1 b a c detail of contacts 0.2 3 min. 3.8 93 2.5 0.2 1.8 0.1 c a 0.1 b 17.8 184 10 4 0.1 0.1 ac b 128.95 a 133.35 2.7 max. 0.15 b a c 6.35 0.1 2.36 1 64.77 ?0.1 c a b 1.27 x 95 120.65 = 2.175 6.62 49.53 92 b 0.13 31.75 1.27 c 0.1 0.4 1) burr max. 0.4 allowed 1) on ecc modules only l-dim-184-30
internet data sheet 34 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules package outlines figure 5 package outline - raw card b 512 mbyte, 2 ranks module 4 c b 0.1 a 0.1 2.36 1 0.1 c 64.77 ?0.1 a b 95 133.35 128.95 1.27 x= 2.175 6.62 120.65 a 6.35 1.27 0.15 4 max. 49.53 92 0.4 31.75 b 0.13 c b 0.1 a c 0.1 detail of contacts 0.2 1.27 3.8 0.13 3 min. 93 0.2 2.5 1 0.05 0.1 ac b 1.8 0.1 b a c 184 10 17.8 burr max. 0.4 allowed l-dim-184-33
internet data sheet 35 rev. 1.11, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules package outlines figure 6 package outline - raw card b 512 mbyte, 2 ranks ecc module l-dim-184-31 1 1 92 92 0.1 1.27 c 4 max. 0.4 a 0.1 b c a 133.35 128.95 a 0.15 b c 0.1 4 b 0.13 31.75 a 64.77 2.36 0.1 ?0.1 6.35 95 x 1.27 = 120.65 6.62 c b 2.175 49.53 0.05 1 1.27 0.2 detail of contacts 0.1 abc 2.5 0.2 17.8 10 184 93 0.13 3.8 3 min. 0.1 1.8 b a 0.1 c 1) burr max. 0.4 allowed 1) on ecc modules only
internet data sheet 36 rev. 1.1 1, 2007 - 01 09152006-1lhy-n6g4 hys[64/72]d[16/32/64][ 300/301/320][g/h ]u?[5/6]?c unbuffered d dr sdram modules table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 current conditions and specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 ac characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
edition 2007-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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